What the filing says, and what it does not

Start with the document, because it is the only hard source in this story. An SEC Form D filed on October 30 reports that PowerLattice has sold $86,009,965 in an equity offering targeting $111,010,000. It records 18 investors and a first sale date of October 15. GeekWire reported the filing on Friday and said the company declined to comment. The filing names neither the investors nor the funding round.

Subtracting the amount sold from the offering target leaves approximately $25 million still to be sold. That is arithmetic from the filing, not a separate fundraising update from PowerLattice. The filing also provides no names for the 18 investors.

Reporting that fills those blanks with guesses would be doing the reader no favors. What can be said is that the new amount is large next to the company's own history: when PowerLattice emerged from stealth last November, it had raised $31 million in total, led by a $25 million Series A from Playground Global and Celesta Capital. Former Intel chief executive Pat Gelsinger, now a general partner at Playground, joined the board. His line from that announcement is still the cleanest statement of the pitch: "AI is not constrained by capital, it's constrained by power."

The demonstration, read on its own terms

Four days before the filing became news, PowerLattice announced a demonstration of what it calls the industry's first monolithic integrated voltage regulator (IVR) chiplet. Its design puts the controller, power transistors and inductors on a single piece of silicon, according to the company.

Conventional power delivery routes current over paths between the power circuitry and processor, creating resistive losses along the way. PowerLattice's approach is to move voltage regulation closer to the processor, inside its package, reducing the distance that current must travel. The company argues that this can improve power-delivery efficiency and leave more of the available power for computation. How large that improvement is in a production accelerator remains the question.

The company says multiple chiplets can be synchronized to behave as one platform, sized to a given accelerator.

The test itself needs its qualifier kept attached. The chiplet powered a high-precision silicon device that PowerLattice developed to emulate the loads and rapid current swings of next-generation AI accelerators. An emulator is a reasonable way to test a power component before a customer integrates it. It is not a customer processor, and the announcement does not present it as one. It also publishes no numbers from the test: no efficiency percentage, no current figure, no transient recovery time, no thermal result. Converge Digest's summary of the release made the same observation, noting the claimed power saving is not a separately verified measurement from this demonstration.

The 50% figure is a claim with a history

The number that will travel furthest from this story is "more than 50%." PowerLattice says its technology reduces total compute power needs by more than half, effectively doubling performance. This is not a new result from October's demonstration. The company made substantially the same claim when it announced its Series A in November 2025, before the latest chiplet demonstration.

The October 26 release repeats the claim but does not publish a measurement showing a 50% reduction. Its demonstration establishes something narrower: the chiplet supplied power to a company-built silicon device designed to emulate the changing electrical loads of next-generation AI accelerators. The release gives no numerical efficiency, current, transient-response or thermal results. The 50% figure remains PowerLattice's standing company claim, not a measured outcome reported from this test.

None of that makes the company uninteresting. Power delivery is a genuine engineering constraint, and the founding team — Peng Zou, Gang Ren and Sujith Dermal — brings experience from Qualcomm, Intel and NUVIA. The company also said last year that engineering samples were in progress for GPUs, CPUs and custom accelerators. The filing now shows $86 million sold in an offering targeting $111 million; it does not disclose what technical results, customer commitments or commercial milestones investors considered when making those investments. But the order of events matters: the 50% claim came first, the latest emulator demonstration came this week, and no public test on a customer accelerator with quantified results has been presented. That is the evidence needed to move the discussion from a promising architecture to a demonstrated technology advantage.

Sources

  1. [1] U.S. Securities and Exchange Commission, Form D — Notice of Exempt Offering of Securities, Powerlattice Technologies Inc., filed October 30, 2026 (primary — read first-hand on EDGAR: total offering amount $111,010,000; total amount sold $86,009,965; $25,000,035 remaining; 18 investors already invested; date of first sale October 15, 2026; issuer incorporated in Delaware in 2023; the filing names no investors and no funding round)Read source
  2. [2] GeekWire, "Filing: Chip startup Powerlattice raises $86M to ease AI's power crunch", October 30, 2026 (reporting of the SEC filing: $86 million raised, $111 million sought, 18 investors, no round or investors named, company declined to comment; prior $31 million total and $25 million Series A; founders, offices and the Gelsinger quote)Read source
  3. [3] PowerLattice, "Powerlattice Demonstrates Industry's First Monolithic IVR Chiplet to Break the AI Power Wall", Business Wire, October 26, 2026 (primary, company-issued — read first-hand: monolithic IVR architecture integrating the controller, power transistors and inductors; PowerMagix inductors; P2A synchronization; the chiplet supplied power to a high-precision silicon device the company developed to emulate next-generation AI accelerator loads; the "more than 50%" figure appears as a description of the technology; no numerical efficiency, current, transient-response or thermal results published)Read source
  4. [4] PowerLattice, "PowerLattice Raises $25 Million to Break the AI Power Wall", Business Wire, November 17, 2025 (primary, company-issued: emergence from stealth; $25 million Series A jointly led by Playground Global and Celesta Capital; $31 million raised to date; the "more than 50%" claim made at that announcement; Gelsinger: "AI is not constrained by capital, it's constrained by power")Read source
  5. [5] Converge Digest, "PowerLattice Demos Monolithic IVR Chiplet for AI Accelerators", October 26, 2026 (secondary — notes the announcement discloses no numerical output current, efficiency, transient recovery time, thermal or process data, and that the test does not establish performance in a commercial accelerator)Read source
  6. [6] Dealroom News, "PowerLattice raises $86M to break AI's power wall", October 30, 2026 (secondary confirmation of the filing figures)Read source