What Google actually gave away
Google has published the RTL for what it describes as its completed 32-bit Coral NPU architecture, alongside an open compiler and simulator. Developers can inspect those artifacts and test supported workflows without relying solely on a performance claim. That is a substantive release of implementation material: the coralnpu, coralnpu-compiler and coralnpu-mpact repositories are all on GitHub today under the Apache License 2.0, and anyone can read them. It does not, by itself, establish that the design is a formally ratified industry standard, that every manufacturing component is included, or that all commercial implementation rights have been verified.
The problem Google says it is solving is also stated plainly in its own post: the edge is split across hundreds of proprietary chip architectures and incompatible toolchains, so teams rewrite kernels and re-quantize models for every chip they target. Coral's answer is a standards-based, ML-first RISC-V design plus one open toolchain, so a team optimizes a model once and deploys it across vendors and power envelopes. Synaptics' adoption gives that pitch a concrete commercial partner, and the public compiler provides a common starting point for developers. What has not yet been demonstrated in the sources reviewed is seamless model portability across different Coral-based chips: the same compiled model, running without device-specific adjustments, with documented compatibility and performance. The open design is a credible foundation for that goal, not proof that the goal has already been reached.
An open chip design becomes more consequential when commercial chipmakers adopt it. Synaptics has announced its SR200 family using second-generation Coral NPU IP, while the earlier Coralboard SL is now generally available through DigiKey. Those are meaningful milestones, but they are three different kinds at once — published code, an available earlier-generation development board, and a newly announced silicon family — and the sources reviewed do not establish that SR200 chips are already shipping to customers.
The numbers that are not measurements
Now separate the figures by what they actually are.
The 10 milliwatt figure is a target, and it is a separate statement from the throughput figure. Google describes a matrix unit configurable for up to 1 TOPS, and separately an architecture targeting 10mW average power for inference. It has not published a measured result establishing that peak throughput and average power occur together on a specified workload or chip, at a specified precision or clock. Read as a pair, the two numbers would imply an efficiency nobody has measured. Neither Google's post nor Synaptics' release publishes a measured power draw for a named workload on shipping silicon.
The 40 percent figure is weaker still. It was quoted at a preview event six days ago, about the M2 design, as a saving against "other processors on the market". The problem is not that the percentage is necessarily wrong; it is that the comparison methodology is undisclosed — no identified baseline processors, no model workloads, no precision, no throughput or measurement conditions. A comparison whose method cannot be examined cannot be checked, repeated responsibly as a finding, or compared with anything a buyer is choosing between.
And the SR200 release itself contains no power number at all. It gives GOPS tiers, memory sizes, CPU cores and connectivity in detail, then describes "unmatched system power efficiency" without a figure attached. For a chip family whose entire pitch is doing more inside a battery budget, the missing number is the story. Pricing is missing too: neither source says what an SR210, SR230 or SR250 costs, or when a customer can order one, beyond Google's "launching this month".
One naming caution belongs here. R&D World also reported that Google described a completed next-generation design called M3, with native 32-bit floating-point support, at the same preview. Google's 20 October announcement describes completion of the 32-bit Coral architecture but does not, in the material reviewed here, explicitly identify that release as M3. The two descriptions should not be treated as an exact product or silicon match without further confirmation — and nothing in either source says an M3-based commercial chip is shipping.
None of this makes the launch hollow. It makes it two launches sharing a date: an openness launch, which is complete and inspectable today, and an efficiency launch, which so far consists of targets and a percentage with an undisclosed method.
What to watch, and what you can do today
If you build edge devices, the actionable item is narrow and real. Developers can inspect Google's published RTL and evaluate the compiler and simulator against supported model workflows. That test is worth more than either company's power claim, because it runs on your model, which is the workload the 40 percent figure never named. Google also says the earlier Coralboard SL is generally available through DigiKey, providing a hardware entry point as of today. That does not establish that every JAX, PyTorch or TensorFlow model will compile unchanged: accepting models from three frameworks is not the same as supporting every operation those frameworks expose. Nor, on the sources reviewed, can the announced SR200 family already be purchased and benchmarked.
For the SR200, the questions to hold until Synaptics answers them are equally narrow: a measured milliwatt figure on a named workload, a price per tier, and an order date. When those three appear, the efficiency story can be judged. Until then, what Google and Synaptics have demonstrably delivered is an open design, an open toolchain, and a newly announced second-generation silicon family built on both. In a market of hundreds of closed toolchains, that is already unusual. It does not need the percentages to be interesting, and the percentages, as published, do not yet earn their place in a buying decision.
Sources
- [1] Google Developers Blog, “Unifying Edge AI: How Coral NPU's open standard brings portable, energy-viable intelligence from model to silicon”, 20 October 2026 — the completed 32-bit architecture, the RTL/compiler/simulator release, the up-to-1-TOPS configuration figure, the “targeting 10mW” wording, the GlobalFoundries 12LP+ iteration figures, and the Coralboard SL general availabilityRead source
- [2] Synaptics, “Synaptics Astra SR200 Series Redefines Edge AI with Vision, Voice, and Display on a Single MCU with High-Density Custom DRAM”, press release, San Jose, 20 October 2026 (read via Edge AI Vision Alliance republication) — the three SR200 tiers and GOPS ratings, memory sizes, CPU cores, Zephyr support, and PSA Level 3 / CC EAL4+ certification targets; no power figure and no priceRead source
- [3] R&D World, “Google teases Synaptics edge AI chip ahead of Oct. 20 launch”, published 16 October 2026, reporting the 14 October Research@ preview — the Coral M2 40 percent and under-6-milliwatt claims with no workloads or comparison processors specified, and the M3 descriptionRead source
- [4] GitHub, google-coral/coralnpu, google-coral/coralnpu-compiler and google-coral/coralnpu-mpact repositories, checked 20 October 2026 — each carries the Apache License 2.0Read source